It has historically been difficult to distribute a well-aligned hardware clock throughout the physical extent of a synchronous processor. One problem with distributing a single clock signal is the different signal delay times which may affect the clock signal as it is distributed to different processors which are different physical distances from the clock source. To solve this problem, synchronous machines often use a clock distribution tree. This enables the physical distance to all the processors to be approximately the same. However, several disadvantages of such a structure exist particularly when it is used in a parallel processing domain. The use of a single clock signal with a vast distribution tree makes it likely that a failure at a single point of the clock tree affects many of the processors relying on the centralized clock signal. Furthermore, such a structure makes it difficult to expand the number of processors being utilized by a single machine, since the tree structure must be modified to accommodate the new processors.